As high-resolution and fast ADC (Analog-to-Digital Converter) and DAC, one that uses a sigma-delta (ΣΔ) modulator has come to be used widely. Sigma-delta conversion in the ADC and sigma-delta conversion in the DAC are in an inverse relationship and this is also true as to MASH (Multistage Noise Shaping), described later. The following DAC is explained as an example.
FIG. 1 is a diagram illustrating an outline of a configuration of a sigma-delta DAC that uses sigma-delta conversion.
As illustrated in FIG. 1, an interpolation filter 12 increases a clock frequency by interpolating input data with a large number of bits based on an OSR (Oversampling Ratio) 11. After that, a sigma-delta modulator (ΣΔMod) 13 converts the data with a large number of bits into data with a small number of bits. After that, a DAC 14 for a small number of bits converts data with a small number of bits into an analog signal and the analog signal is output via an analog low-pass filter 15.
As widely known, the sigma-delta modulator 13 is a converter configured to convert low-speed data with a large number of bits into a high-speed data string with a small number of bits by having information not only in the amplitude direction but also in the time axis direction. Its output is one with a small number of bits, however, has information of high resolution.
FIG. 2A to FIG. 2C are diagrams for explaining the above by frequency regions.
As illustrated in FIG. 2A, data input to the sigma-delta DAC has a spectrum C that repeats in each sampling period of the input data. The spectra C located at the positions of 2π, 4π, . . . are loop-back components by sampling, and therefore, un-usable components. As illustrated in FIG. 2B, the sigma-delta modulator 13 shifts the un-usable loop-back spectra C that are repeated to a spectrum D on the high-frequency side by increasing the sampling frequency. The spectrum D on the high-frequency side is cut by the analog low-pass filter 15 having passing characteristics indicated by E as illustrated in FIG. 2C. By shifting the un-usable loop-back spectra C to the spectrum D on the high-frequency side, the demand for the passing characteristics of the analog low-pass filter 15 is reduced, and thereby, the burden to the analog low-pass filter 15 is reduced. Due to this, it is possible to reduce the burden to an analog circuit the chip area of which tends to increase.
In order to further reduce the burden to an analog circuit, it is desirable to further increase the operating frequency of the sigma-delta modulator.
FIG. 3A and FIG. 3B are diagrams for explaining the effect obtained by shifting repeated spectra toward high frequencies.
As illustrated in FIG. 3A, when the operating frequency of the sigma-delta modulator 13 is low, the loop-back component D by sampling is close to the effective spectrum range in the vicinity of a direct current (DC), and therefore, the high-order analog low-pass filter 15 exhibiting the steep passing characteristics E is desired. In contrast to this, when the operating frequency is high, as illustrated in FIG. 3B, a loop-back component D′ becomes more distant from the DC, and therefore, it is possible to utilize a low-order low-pass filter with less steep characteristics E. Due to this, the burden to the analog circuit is reduced and the chip area can be reduced.
However, there is a limit to the operating speed of the ΣΔ modulator configured by a digital circuit and it is not possible to sufficiently increase the operating frequency.
Non-Patent Document 1 (Mucahit Kizak, et al.) has proposed a MASH (Multistage Noise Shaping) sigma-delta modulator that differentiates an overflow of an adder of an integration unit to obtain its output.
FIG. 4 is a diagram illustrating the configuration of the MASH sigma-delta modulator described in Non-Patent Document 1. The sigma-delta modulator illustrated in FIG. 4 is a three-stage MASH sigma-delta modulator.
As illustrated schematically, the sigma-delta modulator has an integration part S and a differentiation part T. The integration part S has integration units connected in series in the number corresponding to the number of stages of the sigma-delta modulator (three stages in FIG. 4). The integration unit in each stage has each of adders AD0 to AD2 and each of flip-flops (Z−1) SF0 to SF2. Each integration unit performs integration by calculating the sum of the input data and the calculation result one clock before. The overflows of the integration units (the adders AD0 to AD2) are input to the differentiation part T.
The differentiation part T has two differentiation units, two adders TA0 and TA1, and flip-flops MF01, MF02, and MF1. One of the differentiation units has a flip-flop (Z−1) TF1 configured to hold the overflow of the adder AD2 in the third stage of the integration part S in accordance with a clock, and a subtracter TS1 configured to subtract the output of TF1 from the overflow of AD2. MF01 delays the overflow of AD1 in the second stage of the integration part S by an amount corresponding to one clock. TA1 is the adder of the outputs of TS1 and MF1. The other differentiation unit has TF0 configured to hold the output of TA1 and TS0 configured to subtract the output of TF0 from the output of TA1. MF01 and MF02 each delay the overflow of AD0 in the first stage of the integration part S by an amount corresponding to one clock each time in two stages. TA0 is the adder of the outputs of TS0 and MF02. The differentiation unit in each stage performs differentiation by calculating a difference between the data one clock before and the current data.
FIG. 5 illustrates an output waveform when generating an analog output at a fixed DC level in the three-stage MASH sigma-delta modulator in FIG. 4. The operation of the sigma-delta modulator is explained with reference to FIG. 5.
The instantaneous value of the output data is data with a small number of bits in eight levels from −4 to 3. The output data changes at a high speed and its average value can represent high resolution equal to or less than the decimal point. In other words, although the value is a discrete value with a small number of bits instantaneously, the value becomes a value of high resolution in a long period (average). In the frequency region, this is a spectrum in which noise components exist on the high-frequency side in addition to signal components. These noise components are referred to a quantized noise and occur due to an instantaneous high-speed change.
The MASH sigma-delta modulator is widely known, and therefore, more explanation is omitted.
As describe previously, in order to make the quantized noise more distant from the effective spectrum range in the vicinity of the DC, it is desirable to operate the sigma-delta modulator at a high speed, however, in order to do so, it is desirable to operate the integration part S and the differential part T at a high speed. However, the amount of calculation at the integration part S and the differential part T is very large, and therefore, there is a limit to the high-speed operation.